Data processing unit

Details Data processing unit Data processing unit

2001-06-08

2004-04-27

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C711S167000

Reexamination Certificate

active

06728806

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a data processing unit, and more particularly, the invention relates to a data processing unit which controls the temporary storage, error correction, and data transfer after correction of the demodulated data read out and sent from a storage medium, such as a CD-ROM, a music CD, or a DVD-ROM made in conformity to the CD format or the DVD format.
(2) Description of the Prior Art
(General Background Art)
The reading double speed of a DVD-ROM drive or a CD-ROM drive has recently made a great progress. As a result, there is an increasing demand for improvement of performance of the data processing unit used for decryption and error correcting signal processing of DVD format and CD format.
FIG. 1
illustrates a general configuration of a data processing unit such as this. In
FIG. 1
,
1
represents a demodulating circuit which demodulates the physical data read out from an optical disk medium;
2
, a buffer memory serving as a buffer which temporarily stores the demodulated data sent out from the demodulating circuit for error correction and transfer to the outside (hereinafter simply referred to as the “memory” or the “storage means”);
3
, an error correcting circuit which performs error detection by reading out the data stored in the memory, correcting the detected errors, and then writing back the corrected data again into the buffer memory
2
;
4
, an external interface circuit which reads out the corrected data from the buffer memory
2
and outputs the same to an external host PC, an SCSI (small-sized computer interface), or an interface LSI with a standard external bus such as 1394, a kind of i/f specifications;
5
, a bus control circuit which controls the data transfer between a peripheral circuit such as the demodulating circuit
1
, the error correcting circuit
3
, or the external interface circuit
4
and the buffer memory
2
; and
6
, a command processing circuit which teaches the details of command to the above-mentioned components by receiving a command from the outside. (Operation of this circuit will be described later in details under the heading of “The Preferred Embodiments”).
An actual data processing unit has other components such as a wobble signal detection circuit, in addition to the above, and furthermore, the error correcting circuit has a syndrome operator, resulting in a far more complicated structure, however, since these other components do not have a direct relationship with the intent of the present invention, the illustration are explanation thereof are omitted here.
The buffer memory
2
is overwritable, and the data
100
read out first are demodulated by the demodulating circuit
1
, and is rewritten into the correct data as a result of the correction performed on each plural numbers of error correction by the error correction circuit
3
according to necessity. In
FIG. 1
,
100
and
101
represent the signal lines into which data are entered in a more accurate sense of work, however, because such an accurate expression each time might often lead to complications, and rather a simpler representation would not cause any misunderstanding, this shall also apply hereafter in this specification. And, this is also the case with other signals and pieces of the information (or lines thereof) appearing hereafter.
The reading double speed of DVD-ROM drive or CD ROM drive, i.e., the rotating speed of the optical disk is dependent upon the bus band width of this (buffer) memory. This memory generally comprises an SRAM (static random access memory) or a DRAM (dynamic random access memory) as illustrated, however, because it also serves as a cache memory for external output, it becomes necessary to provide a larger capacity, the higher the transfer rate with the outside becomes. Because of this, memory having a high recording density and available at a low cost such as a DRAM is used in many cases.
On the other hand, however, the access speed of a DRAM is lower than that of an SRAM, thereby causing a problem in the performance. Particularly, the data demodulated in the demodulating circuit are divided into usual user's data, error correcting data, and other additional information, and are written separately into the predetermined areas (address spaces) in the memory for each kind of the data. However, because data are not transferred in a predetermined sequence from the demodulating circuit, or may not be transferred at all, the execution of writing into the DRAM will be executed every time the data are transferred as a result, and therefore the high-speed access mode (page mode) of DRAM is not applicable.
(Background art having a particularly close relationship with the problems to be solved by the invention)
Accordingly, in a data processing unit as described above, the bus band width of the memory which temporarily stores the demodulated data for the purpose of error correction and transfer to the outside forms a bottleneck for the system processing performance.
Then, in order to write the demodulated data into the memory as efficiently as possible, it is proposed, for example, to provide a circuit or a memory which temporarily stores demodulated data as divided in terms of the kind of the data in the bus control circuit, and write the data for each kind of the data into the memory by use of the high-speed access mode. This practice may certainly contribute to a higher write efficiency, but will cause an increase in the hardware.
Because of this, there has been an increasing demand for the achievement of a data processing unit permitting efficient write of demodulated data into the memory by addition of only a slight amount of the hardware.
SUMMARY OF THE INVENTION
The present invention was developed in view of the problems as described above, and in the invention, the demodulated data of the same kind are written into a storage means simultaneously, or are written continuously in the transferred sequence, because the data of the same kind are stored in an area within the storage means, and particularly, the continuous data within the same kind are stored in principle in continuous addresses. For this purpose, firstly, a special communication line is provided so that the bus control circuit can recognize the kind of the demodulated data being sent in next in addition to the current modulated data. Secondly, the access requests to the storage means are also adjusted. More specifically, the details are described as follows.
In the first aspect of the invention, the demodulating means sends the data read out from the optical disk and demodulated to the bus control means for the time being in order to store into the storage means for the purpose of error correction or for using as a buffer upon transferring the same to the outside. And, in this occasion, the kind of the data to be demodulated and sent in next is also sent by use of a signal line. The kind of the data is recognized from the number of the data, the signal line, the top code of the sector, the rules of the data storage, etc.
The bus control means temporarily stores the demodulated data currently being sent, the kind of the demodulated data to be sent next, and the information specifying the same in a temporary built-in storage sub-means. When the next data kind information sent in accordance with the first demodulated data is different from a data kind of the first demodulated data currently being sent, the write control sub-means issues a request such that only the first demodulated data be written in the storage means, the write request of the first demodulated data being issued at a good timing.
The expression “issued at a good timing” means issuing a write request promptly, taking account of the time required for the bus control means to adjust write requests from various components, if there is no write request into the storage means of a higher priority, so that the demodulated data having already arrived and currently being sent can be written in the sequence of arrival without waiting for

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