Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-03-09
2003-02-25
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S154000, C711S156000, C711S163000, C711S167000
Reexamination Certificate
active
06526490
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to processing systems.
Processing systems used in aviation and military applications are usually specially built and tested to ensure that they operate predictably. There is, however, increasing pressure on manufacturers to reduce cost of equipment by using commercial off-the-shelf (COTS) components. Commercially available processors are, however, not suitable for use in high integrity applications for several reasons. For example, although the operating system of the microprocessor contains a memory map indicating the location within the memory at which various items of programs and data are stored, the same items of data are not generally located at the same location every time that the processor is turned on. Because data is not located in the same memory partition every time, there can, for example, be no guarantee that data is always contained in memory partitions that have sufficient capacity or that have been tested to the required standard for a particular application. Also, where several different software applications are run on a processor simultaneously, the operating system usually runs the different applications in time-slots, which are usually allocated arbitrarily. This can result in some applications having insufficient allocated time to run reliably every time, whereas less important applications might have more time allocated than is strictly necessary.
In operation, microprocessors function in one of two different modes, namely a User Mode and a Supervisor Mode. Applications programs run entirely in the User Mode whereas the Supervisor Mode is more powerful and is used to provide operating system services to the User Mode and to run the operating system of the processor. Conventional processors switch from the User Mode to the Supervisor Mode either at the end of a time period allocated for a particular application or when the application calls for services from the User Mode. There is generally no indication whether the processor is running in User Mode or in Supervisor Mode. This contributes to uncertainty about the operation of the processor system, which is not acceptable in high integrity systems.
Systems are available that avoid these problems, but these require special fabrication not generally suitable for use with commercially available processors.
BACKGROUND OF THE INVENTION
It is an object of the present invention to provide an improved processing system.
According to one aspect of the present invention there is provided a processing system including a processor, a memory and a monitor, the processor being connected with the memory, the processor including a memory map identifying locations within the memory at which specified data are stored, the memory map being arranged such that data associated with an application are stored at the same location every time an application is run, the processor being arranged to run each application during specified processing time slots, the monitor containing information as to the memory location where data associated with each application are stored and containing information as to the time slots during which the processor should be running each application, the monitor being connected such as to receive signals indicative of the memory locations being addressed and the application being run, and the monitor being arranged to check whether the correct memory locations are being addressed and whether the correct application is being run in a given time slot.
According to another aspect of the present invention there is provided a processing system including an applications processor, a memory and a monitor, the processor being connected with the memory and the monitor, and the processor being operable in two different modes in which it has access to respective different memory locations, the monitor containing a store of at least one keyword, the processor being arranged to supply a keyword to the monitor when it switches between the two different modes, the monitor being operable to compare the keyword supplied by the processor with the keyword stored in the monitor, and the monitor being arranged to deny access by the processor to memory locations associated with a mode if the keyword supplied by the processor is not compatible with the keyword in the monitor.
The memory preferably includes a flash memory containing software relating to the applications to be run on the system and downloadable to other locations in the memory.
A processing system and its method of operation according to the present invention, will now be described, by way of example, with reference to the accompanying drawing.
REFERENCES:
patent: 4104721 (1978-08-01), Markstein et al.
patent: 5854913 (1998-12-01), Goetz et al.
patent: 5968136 (1999-10-01), Saulpaugh et al.
patent: 6055650 (2000-04-01), Christie
patent: 6202130 (2001-03-01), Scales et al.
Davies John Alun
Moore James Frederick
Stevens Peter John
Weale Denis Vaughan
Connolly Bove & Lodge & Hutz LLP
Nguyen Than
Smiths Group PLC
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