Data processing system with memory patching and method thereof

Details Data processing system with memory patching and method thereof Data processing system with memory patching and method thereof

1997-09-25

2000-06-06

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 48, G06F 1200

Patent

active

060732520

ABSTRACT:
A method and apparatus for providing memory patching in a data process system (5). In one embodiment, access control register (32), found in protection registers (20), contains six fields corresponding to six blocks of memory within the ROM (14). Each field includes a patch protect bit (36 and 42) as well as other access protect bits such as read protect and execute protect. The access control unit (28) selectively outputs an access error to the CPU (10) based on the state of the protect bits corresponding to the block of memory being accessed. The patch protect bit, by way of a force patch exception signal (19), alerts the CPU (10) whether the corresponding block of ROM (14) requires a patch. If a patch is required, the maskable address comparator (50) defines the size of the memory patch where the size of the patch can range from a single address location to multiple lines or blocks of contiguous memory.

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