Data processing system with an enhanced cache memory control

Details Data processing system with an enhanced cache memory control Data processing system with an enhanced cache memory control

1995-03-29

1996-03-26

Harrell, Robert B.

Boots, shoes, and leggings

364DIG1, 364DIG2, 364243, 3642434, 36424341, 36424343, 364964, 3649642, 36496421, G06F 1200

Patent

active

055028250

ABSTRACT:
A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.

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