Semiconductor memory device

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307200B, 307279, 307283, 365159, 365184, 365185, 365228, G11C 1140

Patent

active

041432860

ABSTRACT:
A new type of nonvolatile static read/write memory cell constructed with one MOS transistor and one MNOS transistor (4) is disclosed. The MNOS transistor (4) and the MOS transistor (3) together with a load resistor are complementary combined to offer binary states in the .LAMBDA.-shaped I-V curve for memory operation under normal power supply. Upon power failure, the MNOS transistor (4) acts as a backing-up element for nonvolatility. By impressing a control pulse on the drain of the MNOS transistor (4) the MNOS transistor changes from the depletion mode to the enhancement mode, thereby storing the last memory contents before the power failure. The stored nonvolatile memory contents can be easily retrieved. Thus a small size static random access memory is provided. The new cell is characterized by advantageous features such as small cell size, simple peripheral circuit, operation with a unipolar power supply and low standby power consumption.

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Electronics, 4/18/74; pp. 52-53, "Negative Resistance Shown in Dual FET Device".
Tarui et al., "Electrically Reprogrammable Nonvolatile Seiconductor Memory"; IEEE-JSSC, vol. SC-7, No. 5 (10-1972); pp. 369-375.
Cricchi et al., "The Drain-Source Protected MNOS Memory Device and Endurance"; 1973 Int'l Electron Devices Meeting-Technical Digest; pp. 126-129.
Kaneko et al., "On a Novel Static Memory Using CMOS"; Institute of Electronics & Communication Engrs. of Japan; 1/17/74; pp. 19-28.

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