Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-04-25
2008-11-18
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S129000, C711S151000, C711S216000
Reexamination Certificate
active
07454580
ABSTRACT:
A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.
REFERENCES:
patent: 6748501 (2004-06-01), Arimilli et al.
patent: 2006/0026309 (2006-02-01), Day et al.
patent: 2006/0179226 (2006-08-01), Guthrie et al.
Arimilli Ravi K.
Capasso Thomas M.
Cargnoni Robert A.
Guthrie Guy L.
Shen Hugh
Bragdon Reginald G.
Cardwell Eric S
Dillon & Yudell LLP
Handelsman Libby Z.
International Business Machines - Corporation
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