Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-07-13
2008-11-04
Elmore, Reba I (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S140000, C711S210000
Reexamination Certificate
active
07447845
ABSTRACT:
A data processing system includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array, at least one snoop machine that services memory access requests of a remote processor core, and multiple state machines that service memory access requests of the local processor core. The multiple state machines include a first state machine that has a first set of memory access requests of the local processor core that it is capable of servicing and a second state machine that has a different second set of memory access requests of the local processor core that it is capable of servicing.
REFERENCES:
patent: 2002/0087807 (2002-07-01), Gharachorloo et al.
patent: 2004/0139305 (2004-07-01), Arimilli et al.
patent: 2005/0132148 (2005-06-01), Arimilli et al.
patent: 2006/0259707 (2006-11-01), Freytag
Clark Leo J.
Guthrie Guy L.
Starke William J.
Williams Derek E.
Dillon & Yudell LLP
Elmore Reba I
International Business Machines - Corporation
Salys Casimer K.
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