Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-07-13
2008-11-04
Elmore, Reba I (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S140000, C711S210000
Reexamination Certificate
active
07447844
ABSTRACT:
A processing unit includes a local processor core and a cache memory coupled to the local processor core. The cache memory includes a data array, a directory of contents of the data array. The cache memory further includes one or more state machines that service a first set of memory access requests, an arbiter that directs servicing of a second set of memory access requests by reference to the data array and the directory on a fixed schedule, address collision logic that protects memory access requests in the second set by detecting and signaling address conflicts between active memory access requests in the second set and subsequent memory access requests, and dispatch logic coupled to the address collision logic. The dispatch logic dispatches memory access requests in the first set to the one or more state machines for servicing and signals the arbiter to direct servicing of memory access requests in the second set according to the fixed schedule.
REFERENCES:
patent: 2002/0184479 (2002-12-01), Sexton et al.
patent: 2006/0095691 (2006-05-01), Bell et al.
Clark Leo J.
Guthrie Guy L.
Starke William J.
Williams Derek E.
Dillon & Yudell LLP
Elmore Reba I
International Business Machines - Corporation
Salys Casimer K.
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