Data processing system memory controller that selectively caches

Details Data processing system memory controller that selectively caches Data processing system memory controller that selectively caches

1996-04-04

1998-07-07

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711122, 711138, 711168, 711137, G06F 1208, G06F 1300

Patent

active

057784221

ABSTRACT:
An improved memory controller within a data processing system having a look-aside cache architecture is disclosed. The data processing system includes a processor having an upper level cache associated therewith, a memory controller having an associated controller memory, a processor bus coupled between the processor and the memory controller, and a main memory. The data processing system further includes a lower level cache coupled to the processor bus in parallel with the processor and memory controller. According to a first aspect of the present invention, the memory controller includes logic, which in response to receipt of a write request that will not be serviced by the lower level cache and for which the associated data is not a replaced modified cache line, stores the associated data within the controller memory associated with the memory controller, thereby optimizing data storage within the data processing system. According to a second aspect of the present invention, the memory controller includes logic, which in response to receipt of a request for information residing only in main memory, fetches the requested information from main memory and stores additional information adjacent to said requested data in main memory within a prefetch buffer, thereby minimizing access time to the prefetched information.

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Effectiveness of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors, by Fredrik Dahlgren and Per Stenstrom, High Performance Computer Architecture 1995 Symposium.

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