Data processing system having programmable external terminals su

Details Data processing system having programmable external terminals su Data processing system having programmable external terminals su

1996-01-22

1998-04-07

Teska, Kevin J.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

395287, 395293, 711106, G06F 13364

Patent

active

057375844

ABSTRACT:
One or more of control bits (FIG. 7) are formed within a data processor (12) wherein the one or more control bits (FIG. 7) are programmable by the CPU (150) of the data processor (12). When the CPU (150) programs the one or more control bits (FIG. 7) to a first logic state, the one or more chip select control signals which are routed external to the data processor (12) are arbitrated with the external bus. Therefore, the processor (12) must have ownership of the external bus in order to drive the chip selects when operating in this mode of operation. When the CPU (150) programs the one or more control bits (FIG. 7) to a second logic state, the one or more chip select control signals which are routed external to the data processor (12) operate independently of the bus ownership. This ability to select between two modes of operation provides greater flexibility in board level configuration and design.

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Intel ;APX 86/88, 186/188 User's Manual, 1985.

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