Data processing system having direct memory access bus cycle

Details Data processing system having direct memory access bus cycle Data processing system having direct memory access bus cycle

1979-01-31

1981-10-06

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 1300

Patent

active

042939089

ABSTRACT:
In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

REFERENCES:
patent: 3993981 (1976-11-01), Cassarino et al.
patent: 3997896 (1976-12-01), Cassarino et al.
patent: 4025906 (1977-05-01), Riikonen
patent: 4034349 (1977-07-01), Monaco et al.
patent: 4047157 (1977-09-01), Jenkins
patent: 4048673 (1977-09-01), Hendrie et al.
patent: 4067059 (1978-01-01), Derchak
patent: 4093981 (1978-06-01), McAllister et al.
patent: 4110830 (1978-08-01), Krygowski

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