Data processing system having cache memory debugging support...

Details Data processing system having cache memory debugging support... Data processing system having cache memory debugging support...

2006-09-28

2009-06-30

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S206000, C712S205000, C717S129000

Reexamination Certificate

active

07555605

ABSTRACT:
A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.

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patent: 7346744 (2008-03-01), Glasco
patent: 2006/0271919 (2006-11-01), Moyer

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