Boots – shoes – and leggings
Patent
1987-08-20
1990-07-10
Williams, Jr., Archie E.
Boots, shoes, and leggings
3642523, 3642526, 3642549, 3642551, 3642554, 3642555, 3642624, 3642628, 3642598, 3642462, G06F 930, G06F 9308, G06F 9355, G06F 1204
Patent
active
049410857
ABSTRACT:
In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.
REFERENCES:
patent: 3680058 (1972-07-01), DeSantis et al.
patent: 4103329 (1978-07-01), Davis et al.
patent: 4109310 (1978-08-01), England et al.
patent: 4272828 (1981-06-01), Negi et al.
patent: 4466056 (1984-08-01), Tanahashi
Hasegawa Atsushi
Iwasaki Kazuhiko
Kawasaki Ikuya
Nakazawa Takuichiro
Sakamura Ken
Chan Emily Y.
Hitachi , Ltd.
Hitachi Microcomputer & Engineering, Ltd.
Sakamura Ken
Williams Jr. Archie E.
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