Data processing system having an apparatus for de-serialized sta

Details Data processing system having an apparatus for de-serialized sta Data processing system having an apparatus for de-serialized sta

1998-02-17

1999-11-09

Pan, Daniel H.

Electrical computers and digital processing systems: processing

Processing control

Branching

712215, 712207, 711137, 711144, 711145, G06F 938, G06F 930

Patent

active

059833432

ABSTRACT:
An FPSCR (Floating Point Status and Control Register) mechanism supports de-serialized floating point unit (FPU) instruction execution. The FPSCR mechanism provides for speculative execution of all FPU instructions. In particular, instructions that directly alter FPSCR data values may be executed speculatively. Instructions of this type which may be de-serialized include the move-from FPSCR instruction, the move-to-condition register from FPSCR instruction, the move-to FPSCR field immediate instruction, the move-to FPSCR field instruction, the move-to FPSCR bit 0 instruction, the move-to FPSCR bit 1 instruction, as well as FPU register-to-register instructions having a recording bit set. Speculative execution is implemented by providing an accurate working FPSCR at the time the speculatively executing instruction sources FPSCR data. Moreover, the FPSCR mechanism re-establishes the working FPSCR when exceptions occur, or speculative execution is cancelled. The FPSCR de-serialization mechanism is compatible with prior art out-of-order FPU register-to-register instruction execution. By implementing each of these functions, the FPSCR mechanism permits the out-of-order execution of eligible floating point unit instructions.

REFERENCES:
patent: 5463745 (1995-10-01), Vidwans et al.
patent: 5511172 (1996-04-01), Kimura et al.
patent: 5524224 (1996-06-01), Denman et al.
Edited by Cathy May, Ed Silha, Rick Simpson, Hank Warren, The PowerPC Architecture: A Specification for a New Family of RISC Processors, International Business Machines Incorporated, pp. 137-141, 193-196.

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