Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-08-03
2000-06-06
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711213, G06F 1208
Patent
active
060732156
ABSTRACT:
A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue (50) buffers over which a DST access is not allowed. This prevents the cache miss queue (50) from filling up and preventing normal load and store accesses from using the cache miss queue (50).
REFERENCES:
patent: 5206822 (1993-04-01), Taylor
patent: 5694568 (1997-12-01), Harrison, III et al.
Milligan et al., "Processor Implementation Using Queues", 1995, P 58-66, IEEE Micro.
Chan Eddie P.
Ellis Kevin L.
Godsey Sandra L.
Hill Daniel D.
Motorola Inc.
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