Data processing system having a cache and method therefor

Details Data processing system having a cache and method therefor Data processing system having a cache and method therefor

1996-11-14

1999-04-06

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711137, 711144, G06F 1300

Patent

active

058931422

ABSTRACT:
A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.

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