Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2001-12-06
2004-01-06
Butler, Dennis M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S600000
Reexamination Certificate
active
06675311
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an information processor and an information processing system which are controlled by clock signals. More particularly, the present invention pertains to an information processor and an information processing system which are suitable for reducing the clock cycle in order to achieve a high-speed information processing operation.
A first type of conventional information processor controlled by a clock signal is shown in FIG.
2
. The reference numeral
201
denotes a clock oscillator which delivers an original clock signal, while the numeral
202
denotes a clock generator which receives the original clock signal
211
and generates clock signals
212
required to control logic devices
203
to
206
. The reference numeral
213
denotes means for interfacing the logic devices which are controlled by the clocks
212
so as to operate in timed relation to each other.
As the clocks
212
used to control logic devices, it is common practice to employ multi-phase clocks, generally two- or four-phase clocks, which are different in phase from each other. Examples of multi-phase clocks are shown in
FIGS. 4
to
6
.
FIG. 4
shows so-called non-overlap two-phase clocks which have respective time intervals t
1
and t
2
during which both of the clocks are at a low level.
FIG. 5
shows overlap clocks having a duty cycle of 50% which are substantially 90° out of phase with each other.
FIG. 6
shows four-phase clocks having a relatively short pulse width which are substantially 90° out of phase with each other. These clocks are selected in accordance with the form of the logic circuit that constitutes each individual logic device, or with the logic device designing method.
These multi-phase clock signals are generated in the clock generator
202
on the basis of the clock
211
and distributed to the logic devices. No processing of clock signals is carried out in the logic devices. Exchange of data between the logic devices is effected synchronously with the clock signal
211
.
The first problem of this prior art approach is that the multi-phase clock signals
212
must be distributed throughout the information processor. For this reason, the clock skew is usually increased, and the duty cycle of each clock signal is offset from the desired value. This problem is particularly serious when the machine cycle is improved, or reduced, in order to achieve a high-speed information processing operation and the frequency of the multi-phase clock signals
212
is raised. In other words, the greater part of the machine cycle must be spared for the clock skew. On the other hand, the advantage of this prior art approach is that, since one set of multiphase clock signals
212
are distributed throughout the information processor, exchange of data between the logic devices can be effected synchronously.
FIG. 3
shows a second type of conventional information processor that employs a clock signal. The reference numerals
301
,
302
respectively denote clock oscillators,
311
,
312
original clock signals,
303
,
304
information processing units controlled by the clock signals
311
,
312
, respectively, and
313
an interface employed between the information processing units
303
and
304
. This information processor comprises two information processing units which have their respective clock oscillators
301
and
302
. A clock generator which processes an original clock signal to generate multi-phase clock signals such as those shown in
FIGS. 4
to
6
is provided inside each information processing unit. Exchange of data between the information processing units
303
and
304
is effected asynchronously through the interface
313
.
The arrangement of the second prior art approach is often found in microprocessor systems or the like. Each information processing unit corresponds to an LSI chip. The first problem of this prior art approach is that, since the two information processing units are controlled by two different clock signals, the information processing units must be interfaced asynchronously. An asynchronous interface needs to synchronize asynchronous signals and is therefore lower in speed than a synchronous interface. This problem is particularly serious when it is desired to produce a high-speed system in which exchange of data between information processing units is effected a great deal. However, this prior art approach has the advantage that the generation of clock signals is effected inside each information processing unit and, since the clock signals are distributed within one information processing unit, the clock skew can be minimized.
The second problem of this prior art approach is that it is necessary to supply a high-frequency original clock signal from the outside of each information processing unit in order to generate clock signals having a correct duty cycle, it is general practice to frequency-divide an original clock signal inside an information processing unit. Therefore, in the case where the input frequency is halved and the machine cycle is 40 MHz, an original clock signal of 80 MHz must be supplied externally. If a packaged LSI chip is considered to be used as a piece of hardware constituting an information processing unit, it is difficult to supply such an original clock signal from the outside. As the machine cycle is reduced, this problem becomes increasingly serious.
FIGS. 7
to
9
show in combination a third type of conventional information processor controlled by a clock signal. This system is discussed in “Asynchronous Approach for Clocking VLSI Systems” (IEEE Journal of Solid-State Circuits Vol. SC-17, pp. 51 56).
FIG. 7
shows the general arrangement of the prior art approach. The reference numeral
701
denotes an oscillator for delivering a clock signal
711
, and
702
a frequency divider which divides the frequency of the clock signal
711
by N. Information processing units
703
and
704
are supplied with both clock signals
711
and
712
. The numeral
713
denotes an interface circuit provided between the processing units
703
and
704
.
FIG. 8
shows the internal arrangement of the information processing unit
703
. The reference numeral
801
denotes a PLL (Phase Lock Loop) circuit which delays the clock signal
711
so that it is in a specific phase relation with the clock signal
712
. The PLL circuit
801
delivers a clock signal
811
for controlling a logic device
802
. On the other hand, the clock signal
712
is a clock obtained by dividing the frequency of the clock
711
by N, as described above, and it is employed to control an interface circuit
803
. More specifically, the logic device inside the information processing unit is controlled by the high-speed clock signal
711
, while the communication between the information processing units in which it takes a relatively long time to effect signal propagation is controlled by the low-speed clock
712
.
In the case where two different kinds of clock signal are employed, exchange of data between the interface circuit
803
and the logic device
802
involves a problem which is known as metastability. This problem will be explained with reference to FIG.
9
. Let us consider the case where data is delivered from the interface circuit
803
to the logic device
802
. It is assumed that an edge trigger type flip-flop is used to constitute an interface
713
. In the interface circuit
803
, when the clock signal
712
rises from a low level, which is a first potential level, to a high level, which is a second potential level, data is taken in from the interface
713
and delivered to the logic device
802
through a signal bus
812
. In the logic device
802
, when the clock signal
811
rises from a low level to 4 high level, the data delivered is taken in. If the phase relationship between the clock signals
712
and
811
is shifted due to a skew such that the rise of the clock
712
overlaps the vicinity of the rise of the clock
811
(i.e., the portion denoted by the reference symbol t
c
in FIG.
9
), the input of the
Bandoh Tadaaki
Hotta Takashi
Iwamura Masahiro
Kato Kazuo
Kurita Kozaburo
Antonelli Terry Stout & Kraus LLP
Butler Dennis M.
HItachi, Ltd.
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