Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent
1995-09-27
1999-01-12
Coleman, Eric
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
395555, G06F 1200
Patent
active
058601295
ABSTRACT:
A data processing system (10) provides flexibility in interfacing with both a variety of memory devices (56, 58) and external peripheral devices (58). A control register (94) is provided for dynamically controlling a timing relationship between read and write accesses executed by the data processing system. A first set of bits (WP) stored in the control register determines an amount of time a write enable signal is asserted to indicate a length of time required to write a data value to an external device. By recognizing the difference in the timing requirements for read and write operations among different external peripheral devices and memories, as well as the difference in the timing requirements of read and write operations on the same external device, the first set of bits of the control register uses the best timing scheme available to increase the efficiency of the data processing system.
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European Search Report and Communication dated Feb. 19, 1997.
Arends John H.
Kirtland Charles
Moyer William C.
Apperley Elizabeth
Coleman Eric
Motorola Inc.
Toler Jeffrey G.
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