Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-04-17
2001-03-13
Cabeca, John W. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C712S006000
Reexamination Certificate
active
06202130
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to data processing systems, and more particularly to data processing systems which process vector data.
BACKGROUND OF THE INVENTION
A known way to increase the performance of a computer system is to include a local, high speed memory known as a cache. A cache increases system performance because there is a high probability that once the central processing unit (CPU) has accessed a data element at a particular address, its next access will be to an adjacent address. The cache fetches and stores data which is located adjacent to the requested piece of data from a slower, main memory or lower-level cache. In very high performance computer systems, several caches may be placed in a hierarchy. The cache which is closest to the CPU, known as the upper-level or “L1” cache, is the highest level cache in the hierarchy and is generally the fastest. Other, generally slower caches are then placed in descending order in the hierarchy starting with the “L2” cache, etc., until the lowest level cache which is connected to main memory. Note that typically the L1 cache is located on the same integrated circuit as the CPU and the L2 cache is located off-chip. However as time passes it is reasonable to expect that lower-level caches will eventually be combined with the CPU on the same chip.
Recently, microprocessors designed for desktop applications such as personal computers (PCs) have been modified to increase processing efficiency for multimedia applications. For example, a video program may be stored in a compression format known as the Motion Picture Experts Group MPEG-2 format. When processing the MPEG-2 data, the microprocessor must create frames of decompressed data quickly enough for display on the PC screen in real time. The video frame can be represented as a two-dimensional vector, wherein each pixel location corresponds to a unique row and column of the vector. In order to display the data in real time, the microprocessor must process this two-dimensional vector quickly. However conventional microprocessors for desktop applications only contain integer and floating-point scalar processing capability. What is needed then is a data processor for desktop applications which can process vector data quickly as well. This need is met by the present invention, whose features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
SUMMARY OF THE INVENTION
In a data processing system, an instruction for prefetching a vector into a first memory from a second memory which is at a lower hierarchical level than the first memory. In general, the vector comprises n units distributed in the second memory such that each unit is located at an effective address
ea=(ba+(s*i))
where:
ba is the base address of the first unit of the vector;
s is the stride between units of the vector; and
i is an index having a value from 0 to (n−1).
In response to the instruction, a count c is first initialized, then the ea of a cth unit of the vector is calculated. Using this ea, the cth unit of the vector is prefetched from the second memory into the first memory. The count c is then stepped, and, if the count c is a predetermined value with respect to n, the prefetch is repeated for the next unit of the vector. The instruction allows prefetching of the vector in either normal or reversed order, and along a diagonal of a multi-dimensional array.
An object of the present invention is to provide an instruction that explicitly allows all units of a vector to be prefetched into a non-architected memory, such as a level-1 cache, from a lower level memory structure, such as a lower-level cache or main memory.
Another object of the present invention is to provide a vector prefetch instruction that can be halted in response to a change to a different operating mode, and later restarted.
Yet another object of the present invention is to provide a vector prefetch instruction that can be halted in response to a vector prefetch stop instruction.
One other object of the present invention is to provide a method of operation of such a vector prefetch instruction.
REFERENCES:
patent: 4744043 (1988-05-01), Kloker
patent: 4888679 (1989-12-01), Fossum et al.
patent: 5375216 (1994-12-01), Moyer et al.
patent: 5694565 (1997-12-01), Kahle et al.
patent: 5946496 (1999-08-01), Sugumar et al.
Hewlett Packard, “64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture”, Computing Directory Technologies Precision Architecture Document, “MIPS Digital Media Extension”, Rev. 1.0 C-1 through C40 (1997).
Motorola, Inc., “MC88110 Second Generation RISC Microprocessor User's Manual”, pp. 9-29 through 9-30 (1991).
Beavers Bradford Byron
Burgess Bradley G.
Diefendorff Keith Everett
Dubey Pradeep Kumar
Hochsprung Ronald Ray
Cabeca John W.
Motorola Inc.
Polansky Paul J.
Vital Pierre M.
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