Data processing system for controlling operation of a sense ampl

Details Data processing system for controlling operation of a sense ampl Data processing system for controlling operation of a sense ampl

1997-07-30

2000-01-18

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711128, 711167, 365 49, 365205, 365210, G06F 1300, G11C 11413

Patent

active

060165340

ABSTRACT:
A cache memory device having circuitry for controlling operation of a sense amplifier for accessing an array in the data processing system including a cache memory device includes circuitry for enabling the sense amplifier when there is a hit in the array as a result of a read request and disables the sense amplifier when there is a miss in the array as a result of the read request. The cache memory device may receives an address associated with the read request, and compares the address to addresses associated with entries in the array, wherein a hit results when the received address matches at least one of the addresses associated with the entries in the array, and wherein a miss results when the received address does not match at least one of the addresses associated with the entries in the array. The address associated with the read request and the addresses associated with entries in the array are effective addresses. The cache memory device may enable the sense amp only when the array is being accessed by the read request, and only after an entire address associated with the read request has been received.

REFERENCES:
patent: 5018111 (1991-05-01), Madland
patent: 5430683 (1995-07-01), Hardin et al.
patent: 5550774 (1996-08-01), Braver et al.
patent: 5668766 (1997-09-01), Bramnik
patent: 5715426 (1998-02-01), Takahashi et al.
patent: 5848428 (1998-12-01), Collins
patent: 5860127 (1999-01-01), Shimazaki et al.

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