Data processing system for controlling execution of a debug func

Details Data processing system for controlling execution of a debug func Data processing system for controlling execution of a debug func

1997-10-06

2000-02-15

Le, Dieu-Minh T.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 5, 714 29, 714718, G06F 1100

Patent

active

060265019

ABSTRACT:
A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) to have access the same internal registers and memory locations as central processing unit (2). While debug module (10) and central processing unte (2) both have the ability to access the same internal registers and memory locations, central processing unit (2) may not modify a value stored in a plurality of breakpoint registers (50) when an Inhibit Processor Writes to Debug Registers (IPW) bit in a CSR (FIG. 8) of a plurality of control registers (40) is set. The IPW bit may only be modified by a command provided by an external development system (7).

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