Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2008-05-13
2008-05-13
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S168000
Reexamination Certificate
active
11268525
ABSTRACT:
In a data processing system in which a host processing apparatus and a storage subsystem are connected via a channel interface, the present invention makes it possible to expand the number of logical device addresses in excess of the device address limitations of the channel interface, and also enhances the performance of parallel access processing for the same logical device. When an access request is generated for a logical device, the host processing apparatus stores the logical device address to be accessed in a prefix command of a channel command word (CCW) for the access request, sets this CCW in a device information block of a frame which complies with the channel interface, sets a parallel access identifier for identifying a plurality of accesses for the same device in a device address of this frame, and then sends this frame to the storage subsystem.
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patent: 2002/0069306 (2002-06-01), Vishlitzky et al.
patent: 2002/0069307 (2002-06-01), Fairchild et al.
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Hiramatsu Shinichi
Kurokawa Isamu
Muto Jyunichi
Takeuchi Hisaharu
Yasuda Miyuki
A. Marquez, Esq. Juan Carlos
Elmore Reba I.
Fisher Esq. Stanley P.
Hitachi , Ltd.
Reed Smith LLP
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