Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-03-23
2008-11-11
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S141000, C711S144000
Reexamination Certificate
active
07451277
ABSTRACT:
A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping an exclusive access operation, the exclusive access request specifying a target address matching the address tag and indicating a relative domain location of a requester that initiated the exclusive access operation, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and whether a target memory block associated with the address tag is cached within the first coherency domain upon successful completion of the exclusive access operation based upon the relative location of the requestor.
REFERENCES:
patent: 5852716 (1998-12-01), Hagersten
patent: 2007/0204110 (2007-08-01), Guthrie et al.
Guthrie Guy L.
Starke William J.
Stuecheli Jeffrey A.
Williams Derek E.
Bragdon Reginald G.
Dillon & Yudell LLP
Gu Shawn X
International Business Machines - Corporation
Salys Casimer K.
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