Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-01-30
2009-06-02
Ellis, Kevin L (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S135000, C711S144000, C711S156000
Reexamination Certificate
active
07543116
ABSTRACT:
A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to a determination that the combined response indicates that a cached copy of the target memory block may remain in the data processing system, the domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain.
REFERENCES:
patent: 6631447 (2003-10-01), Morioka et al.
patent: 2003/0009635 (2003-01-01), Arimilli et al.
patent: 2006/0179241 (2006-08-01), Clark et al.
patent: 2006/0179249 (2006-08-01), Fields et al.
patent: 2006/0271743 (2006-11-01), Clark et al.
Guthrie Guy L.
Hollaway, Jr. John T.
Starke William J.
Williams Derek E.
Dillon & Yudell LLP
Ellis Kevin L
International Business Machines - Corporation
Parikh Kalpit
LandOfFree
Data processing system, cache system and method for handling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing system, cache system and method for handling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system, cache system and method for handling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4119033