Data processing system, cache system and method for...

Details Data processing system, cache system and method for... Data processing system, cache system and method for...

2005-05-24

2008-12-16

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07467262

ABSTRACT:
In response to execution of program code, a control register within scrubbing logic in a local coherency domain is initialized with at least a target address of a target memory block. In response to the initialization, the scrubbing logic issues to at least one cache hierarchy in a remote coherency domain a domain indication scrubbing request targeting a target memory block that may be cached by the at least one cache hierarchy. In response to receipt of a coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

REFERENCES:
patent: 6415358 (2002-07-01), Arimilli et al.
patent: 2006/0036815 (2006-02-01), Pape

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