Electrical computers and digital processing systems: memory – Address formation – Generating prefetch – look-ahead – jump – or predictive address
Reexamination Certificate
2007-12-25
2007-12-25
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Generating prefetch, look-ahead, jump, or predictive address
Reexamination Certificate
active
11073719
ABSTRACT:
A value of the number of prefetch words is preset by a master device50in a number of prefetch words setting section14of a slave device10. The number of prefetch words refers to the number of data units sequentially receivable by the master device50at a time from the slave device10. When the slave device10receives a read transfer request from the master device50, a prefetch control section13reads from a memory15contiguous data units having a quantity equal to the value of the number of prefetch words, and then writes the contiguous data units into a data buffer12. A bus interface11transmits the contiguous data units stored in the data buffer12to the master device50.
REFERENCES:
patent: 6012106 (2000-01-01), Schumann et al.
patent: 2003/0182513 (2003-09-01), Dodd et al.
patent: 2004/0015622 (2004-01-01), Avery
patent: 2004/0260908 (2004-12-01), Malik et al.
patent: 2000-330929 (2000-11-01), None
LandOfFree
Data processing system and slave device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing system and slave device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system and slave device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3893868