Data processing system and semiconductor memory suited for the s

Details Data processing system and semiconductor memory suited for the s Data processing system and semiconductor memory suited for the s

1994-09-20

1996-11-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523003, G11C 1300

Patent

active

055769977

ABSTRACT:
A data processing system having a logic LSI, a plurality of memory LSIs and a circuit which eliminates delays in the time at which data read out form the memory LSIs reach the logic LSI. The circuit includes variable delay circuits for delaying the data signals read out of the memory LSIs. A control circuit start monitors the time when the data read out of the individual memory LSIs arrive at flip-flops which output the data to the logic LSI. The delay times in the variable delay circuits are controlled by the control circuit for the individual memory LSIs so that the times the data read out from the memory LSIs reach the logic LSI may coincide with a predetermined standard time. Thus, the read data from the individual memory LSIs are caused to reach the flip-flops simultaneously.

REFERENCES:
patent: 5289403 (1994-02-01), Yetter
patent: 5452260 (1995-09-01), Matsui et al.
Hewlett-Packard Journal, "LSI Circuits for Low-End and Midrange PA-RISC Computers, by "C. A. Gleason, et al., Aug. 1992.

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