Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-09-05
2000-10-24
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711122, 711204, 711213, 711137, 711216, G06F 1200
Patent
active
061382094
ABSTRACT:
A data processing system and method thereof utilize a unique cache architecture that performs class prediction in a multi-way set associative cache during either or both of handling a memory access request by an anterior cache and translating a memory access request to an addressing format compatible with the multi-way set associative cache. Class prediction may be performed using a class predict data structure with a plurality of predict array elements partitioned into sub-arrays that is accessed using a hashing algorithm to retrieve selected sub-arrays. In addition, a master/slave class predict architecture may be utilized to permit concurrent access to class predict information by multiple memory access request sources. Moreover, a cache may be configured to operate in multiple associativity modes by selectively utilizing either class predict information or address information related to a memory access request in the generation of an index into the cache data array.
REFERENCES:
patent: 4464712 (1984-08-01), Fletcher
patent: 4797814 (1989-01-01), Brenza
patent: 5014195 (1991-05-01), Farrell et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5235697 (1993-08-01), Steely
patent: 5392414 (1995-02-01), Yung
patent: 5418922 (1995-05-01), Liu
patent: 5530832 (1996-06-01), So et al.
patent: 5564035 (1996-10-01), Lai
patent: 5604753 (1997-02-01), Bauer et al.
patent: 5611071 (1997-03-01), Martinez, Jr.
patent: 5613087 (1997-03-01), Chin et al.
patent: 5623628 (1997-04-01), Brayton et al.
patent: 5717892 (1998-02-01), Oldfield
patent: 5761715 (1998-06-01), Takahashi
patent: 5860104 (1999-01-01), Witt et al.
patent: 5918245 (1999-06-01), Yung
Search results of Dialog Search in Files 351 and 347.
Liu, "Cache Designs with Partial Address Matching", Computer Science Research Report 94A002323, (Mar. 1994).
U.S. Patent application Ser. No. 08/873,785, Multiway Associative External Microprocessor Cache, filed on Jun. 12, 1997.
Krolak David John
Levenstein Sheldon Bernard
Chan Eddie P.
International Business Machines - Corporation
McLean Kimberly
Stinebruner Scott A.
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