Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1998-09-18
2001-01-09
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S041000, C710S046000, C710S047000, C710S120000
Reexamination Certificate
active
06173343
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data processing apparatus comprising a processor and at least one peripheral device and, more particularly, to such apparatus in which the processor is arranged to service the peripheral device either in an interrupt mode in which the peripheral device is serviced in response to interrupt signals generated by the peripheral device or in a timed mode in which the peripheral device is periodically polled and serviced if required, the apparatus having a switching arrangement for switching from the interrupt mode to the timed mode depending upon conditions dynamically determined within the apparatus, at least one of said conditions being that the rate at which the peripheral device generates interrupt signals exceeds a predefined or programmable threshold frequency.
BACKGROUND OF THE INVENTION
A data processing system of the above-described general type is proposed in U.S. Pat. No. 5,414,858. In the computer system described in that patent the latency associated with interrupt processing is said to be relatively high since the interrupt signals initiate operating system routines that are relatively time consuming. On the other hand, the latency associated with polling is said to be relatively low, since the frequency of the polling can be made relatively fast.
In consequence, the patent proposes dynamically switching from an interrupt driven mode to a polling mode in order to reduce latency.
However, the power of modern processors means that the latency associated with interrupt driven processing is sufficiently low so as not to be significant for some applications. Nevertheless, even in powerfull modern computer systems, interrupt processing still involves a performance overhead for the computer, for example since data associated with the task or tasks the computer is performing when it receives the interrupt need to be saved and then restored once the interrupt routine has terminated.
The problem with the approach proposed in U.S. Pat. No. 5,414,858 is that, in at least some applications, the use of fast polling can also use significant processor resources and therefore the dynamic switching approach proposed would not necessarily provide any improvement in overall efficiency.
The object of this invention is to provide an improved technique for managing the servicing of peripheral devices in computer systems and which mitigates the above described drawback of the prior art.
SUMMARY OF THE INVENTION
This invention provides a data processing system of the above described type characterised in that the rate of polling in the timed mode is less than the threshold frequency. In this way, the load on the processor caused by frequent interrupts is reduced.
Thus, dynamic switching between a interrupt driven mode and a timed mode is not used in order to reduce latency, but rather in order to make more efficient use of shared system resources by servicing peripheral devices only periodically at times of high demand.
Such an approach is particularly suitable for Input/Output (I/O) devices which exhibit a wide variation over time in the level of service they require.
In preferred embodiments, the apparatus is arranged to handle, if required, a plurality of service events in each cycle in the timed mode. In this way, the overall number of service events handled is not reduced, rather the handling of the events is scheduled so as to make more efficient use of shared system resources.
In this case, the dynamic switching arrangement can be arranged to switch from the timed mode to the interrupt mode when the number of service events handled within each polling cycle falls below a predefined or programmable threshold.
In one embodiment, the dynamic switching arrangement is arranged to measure the number of service events within each polling cycle and to switch to the interrupt mode when the number of service events handled within each polling cycle is below a predefined or programmable threshold for a predefined or programmable number of consecutive cycles.
Similarly, the dynamic switching arrangement can be arranged, when in the interrupt mode, to measure the time interval between each interrupt and to switch to the timed mode when the time interval between each interrupt is below a predefined or programmable threshold for a predefined or programmable number of consecutive received interrupts.
In one application for which the above technique is particularly suited, the peripheral device is a network adapter including a buffer memory and means to receive and store in the buffer memory frames of data received from a data communications network. In the following, the word frame will be used as a generic term to describe the units in which data is transferred across any particular network, although it will be appreciated that the proper technical term for such units may vary in different network systems. In this case, the service events referred to above are the frames of data received from the network requiring storage in a data storage device. In this implementation, the adapter is settable either to transmit or not to transmit an interrupt signal to the processor whenever a frame of data is received from the network and the switching arrangement comprises means to set the network adapter not to transmit the interrupt signal upon switching to the timed mode.
Viewed from another aspect, the invention also provides a method for operating data processing apparatus comprising a processor and at least one peripheral device, the method comprising servicing the peripheral device either in an interrupt mode in which the peripheral device is serviced in response to interrupt signals generated by the peripheral device or in a timed mode in which the peripheral device is periodically polled and serviced if required, and dynamically switching from the interrupt mode to the timed mode depending upon conditions dynamically determined within the apparatus, at least one of said conditions being that the rate at which the peripheral device generates interrupt signals exceeds a predefined or programmable threshold frequency, wherein the rate of polling in the timed mode is less than the threshold frequency.
Also provided is a computer program product for execution on data processing apparatus comprising a processor and at least one peripheral device to carry out the above-described method.
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patent: 5414858 (1995-05-01), Hoffman et al.
patent: 5471618 (1995-11-01), Isfeld
patent: 5535418 (1996-07-01), Suzuki
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patent: 5896561 (1999-04-01), Schrader et al.
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European Search Report, EP 97 41 0104, Mar. 12, 1998.
IBM Technical Disclosure Bulletin, vol. 38, No. 09A, Sep. 1993, pp 83-84, “Adaptive Polling Algorithm for Monitoring Multi-media Devices”.
Hewlett--Packard Company
Lee Thomas C.
Perveen Rehana
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