Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-01-27
2010-02-02
Peugh, Brian R (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C710S240000
Reexamination Certificate
active
07657709
ABSTRACT:
A data processing system is provided comprising at least one processing unit for processing data; a memory means for storing data; and a cache memory means for caching data stored in the memory means. Said cache memory means is associated to at least one processing unit. An interconnect means is provided for connecting the memory means and the cache memory means. The cache memory means is adapted for performing a cache replacement based on reduced logic level changes of the interconnect means as introduced by a data transfer between the memory means and the cache memory means.
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Karlapalem Sainath
Thomas Bijo
Iannucci Robert
Peugh Brian R
Seed IP Law Group PLLC
ST-Ericsson SA
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