Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-12-22
2001-07-17
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S143000, C710S039000, C710S054000, C710S006000
Reexamination Certificate
active
06263409
ABSTRACT:
CROSS REFERENCE TO CO-PENDING APPLICATIONS
The present application is related to U.S. patent application Ser. No. 08/965,004, filed Nov. 5, 1997, entitled “A Directory-Based Cache Coherency System”; U.S. patent application Ser. No. 08/964,626, filed Nov. 5, 1997, entitled “Memory Optimization State”, now U.S. Pat. No. 6,052,760; (U.S. Pat. Nos. 6,014,709; 6,167,489) U.S. patent application Ser. No. 09/001,592, filed Dec. 31, 1997, entitled “High-Performance Modular Memory System with Crossbar Connections”; U.S. patent application Ser. No. 09/001,588, filed Dec. 31, 1997, entitled “High-Speed Memory Storage Unit for a Multiprocessor System Having Integrated Directory and Data Storage Subsystems”; U.S. patent application Ser. No. 09/001,598, filed Dec. 31, 1997, entitled “Directory-Based Cache Coherency System Supporting Multiple Instruction Processor and Input/Output Caches”;
U.S. patent application Ser. No. 08/964,606, filed Nov. 5, 1997, entitled “Message Flow Protocol for Avoiding Deadlocks”, now U.S. Pat. No. 6,014,709; U.S. patent application Ser. No. 09/218,811, filed Dec. 22, 1998, entitled “System and Method For Bypassing Supervisory Memory Intervention for Data Transfer Between Devices Having Local Memories” now U.S. Pat. No. 6,167,489; and U.S. patent application Ser. No. 09/219,286, filed Dec. 22, 1998, entitled “Method and Apparatus for Scheduling Requests Within a Data Processing System”, all of which are assigned to the assignee of the present invention and incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates generally to the field of data processing systems, and more particularly, to data processing systems that schedule the execution of requests to increase system performance.
Most modem data processing systems include at least one processor and one memory. The processor is typically connected to the memory via a system bus or the like. Other components may also be connected to the system bus including, for example, input/output (I/O) modules, other processors, and/or other memory devices. During normal functional operation of the system, the processor executes a series of commands to accomplish a desired result. Some of these commands can result in requests to the memory, including read requests and write requests. The requests provided by the processor are typically issued in the order of processor execution.
A read request typically provides a read address to the memory over the system bus. The memory reads the requested data from the location identified by the read address and returns the requested data to the processor for subsequent processing. Typically, the processor cannot process further commands until the return data is received by the processor.
In contrast to a read request, a write request typically provides a write address and a write data packet to the memory over the system bus. The memory writes the write data packet to the write address, and no return data is typically expected. Thus for a write request, the processor can typically continue processing further commands immediately after the write request is provided to the system bus and/or memory.
In many systems, the system bus operates at a lower speed than the processor. In addition, more than one system component may compete for the system bus and/or memory. For these and other reasons, the requests issued by the processor may not be immediately serviced by the memory, thereby reducing the performance of the system.
One way to improve system performance is to provide a write queue between the processor and the system. As indicated above, no return data is typically expected for write requests, and the processor can typically continue processing further commands immediately after the write request is provided to the write queue. The write queue is used to temporarily store the write requests until the memory and/or system bus can service the write requests. This frees up the processor more quickly because the write queue, rather than the processor, is left waiting for the system bus and/or memory.
U.S. Pat. No. 5,790,813 to Wittaker discloses a pre-arbitration system and look-around circuit for increasing the throughput of a data processing system by allowing read requests to be executed prior to previously issued write requests so long as the data coherency of the system is not compromised. As noted above, read requests can slow processor throughput by not allowing the processor to process further commands until the read data is returned from the memory. Write requests, on the other hand, typically do not prevent the processor from processing further commands after the write request is issued. Thus, by assigning a higher priority to read requests relative to write requests, Wittaker suggests that the overall throughput of the data processing system may be increased.
While Wittaker provides some increased throughput by assigning a higher priority to read requests, Wittaker does not appear to reduce the overall bus traffic. Rather, it appears each request of Wittaker must eventually be processed over the system bus. It would be desirable to provide a system whereby selected requests can be replaced with substitute requests that perform substantially the same end function, but reduce the overall bus traffic to achieve increased system performance.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages of the prior art by providing a method and apparatus for substituting selected requests with substitute requests that perform the same or similar end function, but achieve increased system performance. Generally, the present invention identifies those requests that have a selected request characteristic. The identified requests are then substituted with substitute requests, wherein the substitute requests perform at least part of the function of the identified requests. The substitute requests are then executed in place of the original identified requests.
In an illustrative embodiment, a data processing system is provided that is configured so that back-to-back execution of two requests of a first request type is faster than back-to-back execution of a request of the first request type and a request of a second request type. Often, because of system and/or memory busing schemes, requests of the same or similar request type can be interleaved more efficiently than requests of different request types.
An identifying block may identify one of the number of requests that has a second request type and that can be successfully converted or replaced with a request of a third request type. The identifying block preferably identifies the identified requests by examining a function code of the requests. The third request type preferably shares a common characteristic with the first request type in that back-to-back execution of a request of the first request type and a request of the third request type is faster than back-to-back execution of a request of the first request type and a request of the second request type.
After the appropriate requests are identified, a substitution block may substitute the identified request with a substitute request of the third request type. The substitute request preferably performs at least part of the function of the second request type. An execution block may then execute selected ones of the number of requests, with the substituted requests replacing the identified requests.
It is contemplated that the identified requests may be write type requests that write unchanged data back to memory. It has been recognized that these types of requests may not need to update the memory contents because the memory already contains a copy of the most current data. Thus, it may be desirable to remove these write type requests or replace them with another request that executes more quickly.
An illustrated system that writes unchanged data back to memory is a multiprocessor data processing system with a directory-based data coherency scheme. In such a system, each processor typically must request and obtain “ownership” of
Haupt Michael L.
Rodi Eugene A.
Crompton Seager and Tufte, LLC
Gossage Glenn
Johnson Charles A.
Starr Mark T.
Unisys Corporation
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