Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-02-10
2008-11-18
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S133000, C711S141000
Reexamination Certificate
active
07454578
ABSTRACT:
A cache coherent data processing system includes a memory and at least first and second coherency domains that each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation targeting a request address allocated to the memory from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains. The master selects the scope based, at least in part, upon whether the memory belongs to the first coherency domain and performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.
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Fields, Jr. James S.
Goodman Benjiman L.
Guthrie Guy L.
Starke William J.
Stuecheli Jeffrey A.
Bragdon Reginald G.
Dillon & Yudell LLP
Gerhardt Diana R.
Gu Shawn X
International Business Machines - Corporation
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