Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1998-06-30
2000-09-12
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711144, 711146, 711207, G06F 1314, G06F 1208
Patent
active
06119204&
ABSTRACT:
A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing. In this manner, the second processor is able to continue normal instruction processing during the process of TLB synchronization.
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Chang Joseph Yih
Hardage, Jr. James Nolan
Nunez Jose Melanio
Petersen Thomas Albert
Chan Eddie P.
Encarnacion Yamir
England Anthony V. S.
International Business Machines - Corporation
Motorola Inc.
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