Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-10-07
1999-07-20
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711141, 711144, 711146, G06F 1208, G06F 1300
Patent
active
059268301
ABSTRACT:
A data processing system and method for maintaining coherency between a high-level (L2) cache and a low-level (L1) cache are disclosed. The L2 (high-level) cache operates in a first mode of operation where a cache line is in a modified and inclusive state, and in a second mode of operation where a cache line is in an invalid and inclusive state. The high-level cache snoops a request from another computing unit for access to data previously stored in the high-level cache. The high-level cache determines if the requested data stored in the high-level cache is invalid or modified, and possibly stored in the low-level cache. If the data is contained in the low-level cache and is modified, the data is returned from the low-level cache to the high-level cache, and from there is written to memory. In the first mode of operation, if no data is returned, and the data in the high-level cache is marked as modified, the data in the high-level cache is written to memory. In the second mode of operation, if no data is returned, the high-level cache does not write any data to memory. In another embodiment, the high-level cache utilizes the state of a line's low-level Inclusive bit when the cache line's MESI (modified, exclusive, shared, invalid) bits are set to the Invalid state. Data in the high-level cache is marked as possibly available in the low-level cache and invalid in the high-level cache. This allows for coherency to be maintained between the high-level and low-level caches without transferring data from the low-level cache to the high-level cache. The high level cache may also resolve collisions between a processor request and a system request originating from another computing unit and avoid sending a RETRY signal to the processor. An efficient pipelined algorithm for flushing the high level (L2) cache and back invalidating the low-level (L1) cache is described.
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Dillon Andrew J.
Gossage Glenn
Henkler Richard A.
International Business Machines - Corporation
Yociss Lisa B.
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