Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1998-11-02
2001-03-27
Choules, Jack (Department: 2777)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C711S115000
Reexamination Certificate
active
06209049
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing system and a method performed by a CPU for inputting data at a prescribed bit width from storage devices, such as flash ROM, in a data processing system.
2. Description of the Prior Art
Conventional data processing systems provided with a CPU include a program ROM for storing control programs used by the CPU to execute prescribed control processes: data ROM for storing data to be referenced during those control processes: RAM that serves as a work area during those control processes for performing input and output of data; I/O interface for executing in hardware data input and output between external devices; and the like.
Each of these storage devices contains storage space that can be accessed by the CPU. Addresses are assigned for the storage spaces of each storage device such that the addresses do not overlap. The CPU can access each of the storage devices by outputting the relevant address data.
However, the storage space contained in individual storage devices is generally smaller than the total address space that can be accessed by the CPU. Therefore, an address decoder is normally positioned between the CPU and the storage devices. The address decoder executes processes to generate the address of each storage device based on address data outputted from the CPU.
Occasionally, the width of the I/O data bus used by the CPU is different from that of the data bus for the storage devices. Therefore, some conventional systems employ a configuration in which a plurality of storage devices are arranged together and made to conform to the I/O data width of the CPU using the address decoder.
For example, a 32-bit CPU has a 32-bit data bus. However, the data buses in the program ROM and data ROM currently have a maximum width of 16 bits. Hence, conventional systems have used the two ROM devices together to form a 32-bit data bus width.
However, this configuration can be wasteful because it necessitates that two ROM devices be always provided, regardless of how small the necessary ROM capacity is. Printing devices, for example, can be mounted with data ROM for storing various user-specific data based on user requests. For a user who only prints on special thick paper, for example, modifiable data is stored in the data ROM to indicate the fixing temperature should be higher than normal. In addition, special font data may be stored in the data ROM for users who print characters of special languages.
The size of this user-specific data can change drastically according to specifications of the user. One user may require about 1 MB of data, while another can get by on about 0.5 MB of data.
When 1 MB of data is required, it is possible to provide two ROM memories of 0.5 MB each. However, for the user that only requires about 0.5 MB of data, it will still be necessary to provide two ROM memories of 0.5 MB, due to the CPU data bus width problem described above. It is very difficult to find flash memory in sizes less than 0.5 MB.
Various methods can be considered to overcome this problem, such as changing the hardware configuration for each user or changing the software configuration so that data input to the CPU is performed at a lesser data bus width. However, changes in the hardware and software configurations can be expensive.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention to provide a data processing system and particularly a method of inputting data from storage devices in the data processing system, in order that accesses to the storage devices can be performed at either the same data bus width as the system data bus width or a width smaller than the system data bus width without changing the hardware and software configurations.
This and other objects of the present invention will be attained by a data processing system including a data processing device for switching a process data input mode for each prescribed area in the total address space between a first mode, in which data is input at a first number of bits, and a second mode, in which data is input at the first number of bits by performing a plurality of inputs at a second number of bits smaller than the first number of bits; storage devices for outputting process data at the second number of bits; and an address data converter for converting address data for the storage devices.
The data processing device includes an address data output device used to output address data for selecting an external device having a prescribed area allocated in the total address space; a storage device number determination device for determining the number of storage devices; and a process data input device for inputting process data from the storage devices, using either a first address area by the first mode or a second address area by the second mode, based on the results of the determination performed by the storage device number determination device. The address data converter includes an address data extraction device for extracting necessary address data and outputting the necessary data to the storage devices based on whether the address data from the data processing device corresponds to the first or second area of memory, in order to effect either the output of process data from a plurality of storage devices equivalent to the first number of bits or process data output at the second number of bits; and a selecting device for outputting signals based on the address data to select the storage devices. The storage devices are connected to at least one of connection devices that connect to the address data extraction device via an address data line and the data processing device via a process data line.
With this construction, when it is determined according to the storage device number determination device of the data processing device that the number of storage devices is a number at which process data can be input at the first number of bits, then the process data input device inputs process data from the storage device in the first mode using the first address area. That is, address data corresponding to the first address area is output from the data processing device. The address data converter employs the address data extraction device to extract address data needed to induce a plurality of storage devices to output process data equivalent to the amount of the first number of bits, and outputs the address data to the storage device. Based on this address data, the selection device outputs a selection signal for selecting the storage devices. In response, the storage devices output process data equivalent to the first number of bits.
On the other hand, if the storage device number determination device of the data processing device determines that the number of storage devices is not capable of inputting process data at the first number of bits, process data is input from the storage devices in the second mode using the second address area. That is, address data corresponding to the second address area is output from the data processing device. The address data converter employs the address data extraction device to extract address data needed to induce a plurality of storage devices to output process data equivalent to the amount of the second number of bits, and outputs the address data to the storage device. Based on this address data, the selection device outputs a selection signal for selecting the storage devices. In response, the storage devices output process data equivalent to the second number of bits. Since the data processing device outputs address data several times, the input is performed several times at the second number of bits. Therefore, input at the first number of bits is achieved through several inputs at the second input of bits.
In this way, input at the first number of bits is accomplished by inputting a number of bits that suits the number of storage devices connected to the connection device, which in turn is connected to the data processing device via a proc
Brother Kogyo Kabushiki Kaisha
Choules Jack
Pitney Hardin Kipp & Szuch LLP
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