Data processing system and method for improving performance of d

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor

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326 96, 326 98, H03K 19096, H03K 1900

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active

056465572

ABSTRACT:
A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit for a predetermined portion of a clock cycle. The output circuit may also include a pair of control transistors to allow the output latching circuit to be turned off during the evaluate portion of the clock cycle thus improving the speed of the domino logic circuit. During the first half of the reset portion of each cycle, the output latching circuit is active and allows the circuit to retain its output state. During the time the passgates are turned off, the evaluate circuit is disconnected and may begin resetting. During the second half of the reset portion of the clocking signal, the passgates open, which allows the output stage to be reset. Since the two additional transistors in the output circuit are controlled by the same signals which control the passgates, the circuit is relatively cheap since only the two transistors must be added to the circuit.

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IEEE Journal of Solid-State Circuits, "Design-Performance Trade-Offs in CMOS-Domino Logic," v sc-21 n2, Apr. 1986, Oklobdzija et al.
IEEE 1985 Custom Integrated Circuits Conference, "Design-Performance Trade-Offs in CMOS Domino Logic" Oklobdzija et al.
Comput. & Elec. Engng., "An Improvement for Domino CMOS Logic," v13 n1, 1987, pp. 53-59., Zhang.

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