Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1995-07-31
1997-07-08
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326 96, 326 98, H03K 19096, H03K 1900
Patent
active
056465572
ABSTRACT:
A domino logic circuit includes an evaluation circuit for receiving input signals and performing a logic operation on the input signals, a passgate circuit for controlling the transmission of signals to an output circuit and a feedback latch circuit for holding the output of the evaluation circuit for a predetermined portion of a clock cycle. The output circuit may also include a pair of control transistors to allow the output latching circuit to be turned off during the evaluate portion of the clock cycle thus improving the speed of the domino logic circuit. During the first half of the reset portion of each cycle, the output latching circuit is active and allows the circuit to retain its output state. During the time the passgates are turned off, the evaluate circuit is disconnected and may begin resetting. During the second half of the reset portion of the clocking signal, the passgates open, which allows the output stage to be reset. Since the two additional transistors in the output circuit are controlled by the same signals which control the passgates, the circuit is relatively cheap since only the two transistors must be added to the circuit.
REFERENCES:
patent: 3646369 (1972-02-01), Fujimoto
patent: 4700086 (1987-10-01), Ling et al.
patent: 4780626 (1988-10-01), Guerin et al.
patent: 4849658 (1989-07-01), Iwamura et al.
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5041742 (1991-08-01), Carbonaro
patent: 5065048 (1991-11-01), Asai et al.
patent: 5070262 (1991-12-01), Hashimoto
IEEE Journal of Solid-State Circuits, "Design-Performance Trade-Offs in CMOS-Domino Logic," v sc-21 n2, Apr. 1986, Oklobdzija et al.
IEEE 1985 Custom Integrated Circuits Conference, "Design-Performance Trade-Offs in CMOS Domino Logic" Oklobdzija et al.
Comput. & Elec. Engng., "An Improvement for Domino CMOS Logic," v13 n1, 1987, pp. 53-59., Zhang.
Runyon Stephen Larry
Schorn Eric Bernard
England Anthony V. S.
Galasso Raymond M.
International Business Machines - Corporation
Roseen Richard
Westin Edward P.
LandOfFree
Data processing system and method for improving performance of d does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing system and method for improving performance of d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing system and method for improving performance of d will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2410816