Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2000-01-21
2004-02-03
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S233000, C712S234000
Reexamination Certificate
active
06687813
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method and an apparatus for implementing zero overhead loops, and more particularly to a method and an apparatus for implementing zero overhead loops using a prefix word in data processing units having a pipelined architecture.
BACKGROUND OF THE INVENTION
Data processing units have a looping capability that allows a sequence of instructions (i.e.—loop code) to be repeated a predetermined number N of times by jumping from the last instruction of the loop code to the first instruction of the loop code, if the loop was iterated for less than N times. Data processing units having a pipelined architecture, execute an instruction in a number of steps, such as fetch, decode and execute. In this type of data processing unit the first instruction of the loop code can be fetched while the last instruction of the loop code, is executed.
Performing the conditional jump can be done by using special hardware which detects that the last instruction of the loop code is executed. Usually the special hardware included a plurality of registers, a subtraction unit (i.e.—decrementor) and a comparator, for detecting if when the loop was iterated N, N is usually stored within one of the plurality of registers.
Performing the conditional jump can also be done by adding a special bit to each instruction, this bit indicating that there is a need to perform the conditional jump. U.S. Pat. No. 5,727,194 of Shridhar describes a system and a method for implementing zero overhead loops, using a special bit. A disadvantage of this solution is a decrease in the code density. Furthermore, in many prior art instruction sets, it is not possible to dedicate a special bit in each instruction of a processors instruction set. Another solution is setting such a special bit in a subset of the instruction set, but such a solution is not practical. A further disadvantage of the method disclosed in U.S. Pat. No. 5,727,194 of Shridhar, was that it did not deal with nested loops, and especially nested loops where an inner loop and an outer loop ended at consecutive instructions.
The method disclosed in U.S. Pat. No. 5,727,194 required that the penultimate instruction of the loop code will have a bit which will initialize a conditional jump to the beginning of the loop code, thus there was a need to place at least two instructions between the end of two loop codes. If the bit was assigned to another instruction, there was still a need to have a plurality of instructions between the end of two loop codes.
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“The TMS320C30 Floating-Point Digital Signal Processor” by Panos Papamichalis and Ray Simar, Jr., IEEE Micro, (Dec. 8, 1988) No.6+index, New York, USA, pp. 13-29.
Benayahu Noam
Hazan Gilad
Norman Oded
Gaffin Jeffrey
Knapp Justin
Motorola Inc.
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