Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-10-01
2001-10-16
Kim, Matthew (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S203000, C711S205000, C711S207000, C711S208000
Reexamination Certificate
active
06304951
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to data processing systems and, in particular, to a data processing system having a virtual memory address space for generating virtual memory descriptors which are utilized to efficiently access a main memory. Still more particularly, the present invention relates to a method and system in a data processing system having a virtual memory address space for generating virtual memory descriptors including pretranslated physical addresses for accessing a main memory.
2. Description of the Related Art
Personal computer systems are well known in the art. They have attained widespread use for providing computer power to many segments of today's modern society. Personal computers may be defined as desktop systems, floor standing systems, or portable microcomputers. Examples of such personal computer systems are IBM's PC series, Aptiva series, and Thinkpad series.
Many computer systems include a virtual memory address space which permits an application or process to address a space which is larger than the main memory included within the system. In virtual memory systems, it is necessary to translate virtual addresses into physical addresses in order to execute commands. One common method for performing the translations is to perform a page table look-up.
The virtual address space is typically divided into equal sized pages. A page table is maintained which includes a physical address for the first byte of main memory for each page of the virtual address space. The page table is stored in main memory and is accessed each time a virtual address is included within a command. In this manner, each time a virtual address is encountered, the physical address must be determined.
The physical address is determined utilizing a page table typically by taking a number of the upper bits of the virtual address to determine an associated page of virtual memory. The lower ordered bits are utilized as an offset into the page to locate the starting physical address for the particular virtual address. Therefore, for each virtual address, the page table must be accessed to determine the starting physical address for the associated page. Thereafter, the starting physical address must be added to the offset to determine the physical address which is associated with the virtual address of interest.
Some virtual memory systems utilize a descriptor-based addressing scheme. In these systems, each command which needs to access a virtual memory address must utilize a memory descriptor to do so. The memory descriptor includes information which tells the virtual memory manager of the system how to address the location in a virtual sense. Typically, the descriptor will include a segment identifier which identifies a particular virtual memory segment.
Once the memory descriptor is utilized to obtain the necessary virtual memory addressing information, the virtual address must be translated to a physical address for each command.
For example, a system may often need to perform several input/output commands. These commands may be implemented utilizing direct memory access (DMA) commands. When a DMA command is executed, the virtual address included within the command must be translated into the appropriate physical address. This process of translating addresses must be performed for each command.
In some systems, the timing of the execution of commands is critical. For example, multimedia systems require the delivery of data within a deadline in order to maintain an accurate audio and/or video output. The process of translating virtual addresses into physical addresses for each I/O command will degrade the performance of the system.
Therefore a need exists for a method and system in a data processing system having a virtual memory address space for generating a virtual memory descriptor including pretranslated physical addresses utilized to access a main memory.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide a method and system in a data processing system having a virtual memory address space for generating virtual memory descriptors which are utilized to efficiently access a main memory.
It is yet another object of the present invention to provide a method and system in a data processing system having a virtual memory address space for generating virtual memory descriptors including pretranslated physical addresses for accessing a main memory.
The foregoing objects are achieved as is now described. A data processing system and method are described for generating virtual memory descriptors which include pretranslated physical addresses. The data processing system has a virtual memory address space and a main memory. The main memory includes a first plurality of physical addresses. A temporary association is established between a region of the main memory and a segment of the virtual memory address space. The region of main memory is addressed utilizing a second plurality of physical addresses. The segment of virtual memory is addressed utilizing a plurality of virtual addresses. In response to the establishment of the temporary association, a virtual memory descriptor is generated and is utilized to address the segment. Each of the plurality of virtual addresses is translated to one of the second plurality of physical addresses. Each translated one of the second plurality of physical addresses is stored in the memory descriptor. The plurality of virtual addresses are translated to the second plurality of physical addresses and stored prior to the virtual memory descriptor being utilized to access the main memory.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
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patent: 5960466 (1999-09-01), Belgard
patent: 6049857 (2000-04-01), Watkins
Mealey Bruce Gerard
Swanberg Randal Craig
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Kim Matthew
Leeuwen Leslie A. Van
Vital Pierre M.
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