Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Patent
1997-04-25
1999-11-09
Lim, Krisna
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
712219, 712201, 712205, G06F 906, G06F 922
Patent
active
059833416
ABSTRACT:
A data processing system indicates that an instruction does not have available data because of a cache miss or because of a non-cache-miss delay. When the instruction is not able to access the available data and a cache miss results, instructions which are dependent on the issued instruction are not issued. However, if the load execution is delayed because of a non-cache-miss delay, then the instructions which are dependent on the issued instruction are also issued in anticipation of a successful load instruction execution in a next timing cycle. Through the use of this issuing mechanism, the efficiency of the data processing system is increased as an execution unit is better able to utilize its pipeline.
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Cheong Hoichi
Jordan Paul Joseph
Le Hung Qui
England Anthony V. S.
International Business Machines - Corporation
Kordzik Kelly K.
Lim Krisna
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