Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-02-10
2008-12-16
Bragdon, Reginald G. (Department: 2189)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S127000, C711S154000, C711S156000, C714S006130, C714S006130, C714S723000
Reexamination Certificate
active
07467323
ABSTRACT:
A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
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Fields, Jr. James Stephen
Ghai Sanjeev
Maule Warren Edward
Stuecheli Jeffrey Adam
Bragdon Reginald G.
Dillon & Yudell LLP
Gerhardt Diana R.
Gu Shawn X
International Business Machines - Corporation
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