Data processing system and method for efficient L3 cache...

Details Data processing system and method for efficient L3 cache... Data processing system and method for efficient L3 cache...

2007-12-13

2009-02-10

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S122000, C711S144000, C711S156000

Reexamination Certificate

active

07490202

ABSTRACT:
A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.

REFERENCES:
patent: 7337280 (2008-02-01), Guthrie et al.

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