Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-02-10
2008-11-18
Bragdon, Reginald G. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S141000, C711S145000
Reexamination Certificate
active
07454577
ABSTRACT:
A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.
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Fields, Jr. James Stephen
Goodman Benjiman Lee
Guthrie Guy Lynn
Starke William John
Williams Derek Edward
Bragdon Reginald G.
Dillon & Yudell LLP
Gerhardt Diana R.
Gu Shawn X
International Business Machines - Corporation
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