Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1998-05-12
2001-02-06
Lee, Thomas C. (Department: 2787)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C710S031000
Reexamination Certificate
active
06185692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to a method and system for data processing and in particular to a method and system for selecting a bus clock frequency of a data processing system. Still more particularly, the present invention relates to a method and system for dynamically setting the bus clock frequency of a data processing system in response to a number of loads.
2. Description of the Related Art
As microprocessor technology has continued to advance, the user's perception of the performance of a personal computer system is less determined by the clock frequency at which the central processing unit (CPU) operates and more determined by the data communication capabilities of the personal computer system. In a typical personal computer system, which may contain a CPU, one or more levels of memory, and a number of adaptor cards all coupled by one or more buses, the data communication capabilities of the personal computer system are determined in large measure by the throughput of the selected bus architecture. The throughput of the selected bus architecture is determined, in turn, by a number of factors, including the bandwidth of the bus, the bus clock frequency, and the overhead of the bus communication protocol.
Naturally, in order to enhance the performance of a computer system, it is desirable to increase the throughput of the selected bus architecture by increasing the bus clock frequency and/or bandwidth while decreasing the bus communication protocol overhead. One primary limitation on bus clock frequency is the number of loads connected to the bus. For example, the bus clock for a PCI (Peripheral Component Interconnect) local bus is permitted by the PCI specification to operate at any frequency between 0 and 66 Megahertz (MHz), but can only operate at maximum frequency if the PCI local bus has three or less loads. Otherwise, the PCI local bus is constrained to operate at a lower frequency. As a result, the current industry standard operating frequency for PCI local buses is 33 MHz, at which speed a PCI local bus can support up to ten loads.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved method and system for data processing.
It is another object of the present invention to provide an improved method and system for selecting a bus clock frequency of a data processing system.
It is yet another object of the present invention to provide a method and system for dynamically setting the bus clock frequency of a data processing system in response to a number of loads.
The foregoing objects are achieved as is now described. A data processing system is provided that includes a bus, one or more loads coupled to the bus, and a clock generator. The clock generator generates a bus clock signal that is coupled to at least one of the loads. While the clock generator is generating a bus clock signal having a first frequency, the number of loads connected to the bus is determined. In response to this determination, the frequency of the bus clock signal is automatically changed from the first frequency to a second frequency. In one embodiment in which the bus is a PCI local bus having a plurality of slots, the determination of the number of loads is made by examining at least one storage location associated with each of a plurality of slots.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5491814 (1996-02-01), Yee
patent: 5761461 (1998-06-01), Neal
patent: 5778194 (1998-07-01), McCombs
patent: 5809291 (1998-09-01), Munoz-Bustamante
patent: 5815734 (1998-09-01), Lee
Dillon Andrew
Grosser George E.
International Business Machine Corporation
Lee Thomas C.
Patel Nitin
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