Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-09-06
2005-09-06
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S752000, C714S052000, C714S054000, C714S042000
Reexamination Certificate
active
06941505
ABSTRACT:
A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be intended for a software ECC process. Since ECC codes are added to the partial storage area alone and an error correction is made thereto to thereby increase the number of rewrite assurances, substantially needless waste of each storage area by ECC codes can be avoided as compared with a configuration in which the ECC codes are added to all the write data without distinction regardless of the storage areas. Further, since software copes with ECC processing, ECC correcting capability matched with a device characteristic of the non-volatile memory can easily be selected.
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Ikehashi et al., “A 60ns Access 32kByte 3-Transistor Flash for Low Power Embedded Applications,” 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp 162-165.
Hiraki Mitsuru
Ishikawa Eiichi
Shukuri Shoji
Yada Naoki
De'cady Albert
Gandhi Dipakkumar
Hitachi , Ltd.
Miles & Stockbridge P.C.
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