Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-01-31
2004-04-13
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S035000, C710S105000, C713S400000, C370S464000
Reexamination Certificate
active
06721832
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-025475, filed Feb. 2, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a data processing system and a bus cycle control method, and more particularly to a data processing system for handling various types of data, including audio/video data, other data, and programs, and a bus cycle control method used in the system.
With recent advances in computer technology, various digital information devices such as multimedia-compatible personal computers, set top boxes, digital TVs, and game machines have been developed. Digital information devices of this type are required to have the ability to handle various media such as broadcasting media, communication media, and storage media.
Therefore, personal computers are required to have not only the function of processing ordinary programs but also the function of dealing with AV (audio/video) stream data needing real-time processing. On the other hand, consumer AV devices such as set top boxes, digital TVs, and game machines are required to have the function of handling computer data, that is, programs and data other than A/V stream data, to implement interactive title playback using software control.
Since the bus cycle used in computers was designed to transfer the computer data exactly, it was unsuitable for the transfer of AV stream needing great band widths. For example, in a PCI (Peripheral Component Interconnect) bus, because the master and target operate while each monitoring the state of the ready signals (IRDY, TRDY) from the other party, they have to do handshaking in each clock cycle. One clock cycle on the PCI bus is about 30 ns (when the clock frequency is 33 MHz). In the handshaking operation, the master and target check the state of the ready signal from the other party and determine the operation in the next clock cycle. They are required to do such handshaking during one clock cycle.
Although the presence of such handshaking assures the reliability of the computer data, it might hinder the improvement of the band width of AV stream. The reason is that since AV data has almost no effect on the sense of sight and hearing of users because of its characteristics, even if part of the data has been lost, it is not required to have as high reliability as that of computer data.
Furthermore, in the PCI, resources (containing memory addresses, I/O addresses, or the like) of a CPU are used for addressing. Even when direct data exchange between the devices on the PCI bus is more efficient, the data is usually transferred via the CPU and memory. In the addressing method using the resources (containing memory addresses, I/O addresses, or the like) of the CPU, the register specifications and the like for the devices to be accessed are required to be clearly determined. Thus, the method is unsuitable for direct communication between devices differing in manufactures.
On the other hand, conventional AV devices were cascade-connected in the order in which the AV stream was processed, thereby physically making a peer-to-peer connection between devices handling the AV stream. Basically, the AV stream was not entered into the CPU. With the advent of titles into which the AV stream and interactive commands have fused, the CPU has recently been required to process the stream as the need arises. This makes it more difficult to make a physical peer-to-peer connection between devices as before. To overcome the difficulty, efforts have begun to be made to grope for a bus connection capable of implementing a flexible processing system.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a data processing system capable of transferring stream data efficiently on an existing bus such as a PCI bus, and a bus cycle control method.
According to one aspect of the present invention, there is provided a data processing system comprising: a bus; a plurality of devices connected to the bus; and means for executing data transfer between at least two of the plurality of devices via the bus, using one of a first bus cycle mode that enables data transfer with handshaking operation therebetween and a second bus cycle mode that enables stream data transfer without handshaking operation therebetween.
According to another aspect of the present invention, there is provided a data processing system comprising: a bus; a plurality of devices connected to the bus; a system memory; and means for executing data transfer between at least two of the plurality of devices via the bus, using one of a first bus cycle mode that enables data transfer through the system memory and a second bus cycle mode that enables stream data transfer without passing through the system memory.
According to still another aspect of the present invention, there is provided a bus cycle control method applied to a data processing system in which data is transferred between devices via a bus, bus cycle on the bus being constituted by an address phase that specifies a type of the bus cycle and an address, and one or more data phases following the address phase, the method comprising the steps of: outputting onto the bus in the address phase a command indicating execution of an expansion bus cycle mode that enables stream data transfer without handshaking operation between the devices; changing the bus cycle from an ordinary bus cycle mode that enables data transfer with handshaking operation between the devices to the expansion bus cycle mode; and executing stream data transfer between devices via the bus without handshaking operation therebetween by the expansion bus cycle mode.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.
REFERENCES:
patent: 5029124 (1991-07-01), Leahy et al.
patent: 5717954 (1998-02-01), Grieff et al.
patent: 5751987 (1998-05-01), Mahant-Shetti et al.
patent: 5974467 (1999-10-01), Haddock et al.
patent: 6088366 (2000-07-01), Sung
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Ray Gopal C.
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