Computer graphics processing and selective visual display system – Computer graphics display memory system – Logical operations
Reexamination Certificate
2001-07-27
2004-12-14
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Logical operations
C345S531000, C345S539000, C345S559000, C345S567000, C718S108000
Reexamination Certificate
active
06831654
ABSTRACT:
This application claims the benefit of United Kingdom Application No. 0103472.7 filed Feb. 13, 2001.
FIELD OF THE INVENTION
The present invention relates to control of data transfer in a data processing system generally and, more particularly, to a method and apparatus for transferring or copying blocks of data between memory locations in a data processing system. The invention may be particularly useful in the transfer (or copying) of blocks of graphics data utilizing a block move engine (BME).
BACKGROUND OF THE INVENTION
The use of block move engines (also known as “bit blitters” or “blitting engines”) for rapidly copying blocks of graphics data between memory locations in data processing systems is a well established technique for graphics processing. Operation of a BME can involve the setting up of many BME control registers by a central processing unit (CPU) to define the task which the BME is intended to perform. Such tasks can be repetitive or involve steps which alternately take a long or short time to run. However, the CPU must wait for each task to finish before setting the registers for the next task.
Referring to
FIG. 1
, a data processing system
100
incorporating a BME for graphics processing is shown. The data processing system
100
includes a CPU
102
and a memory
104
, each connected to a system bus
106
. A BME
108
is also connected to the system bus
106
for reading and writing data to and from the memory
104
. A plurality of control registers
110
are configured to control the BME
108
and determine the processing task or tasks that the BME
108
is to perform.
The control registers
110
are connected to the CPU
102
via a data link
112
. The CPU
102
transmits data to the control registers
110
which defines an operation of the BME
108
. Once correctly set up by the CPU
102
, the control registers
110
effectively contain a set of instructions for controlling the operation of the BME
108
. The BME
108
is then able to access blocks of graphics data stored in the system memory
104
. The BME
108
can combine blocks of data and write the blocks back to the memory
104
(or copy them from one location in memory to another). A series of instruction sets written in the control registers
110
have a number of steps that (i) are repetitive or (ii) alternatively require varying degrees of time for the BME
108
to perform. Once all of the steps in the set of instructions have been performed by the BME
108
, a signal TASKEND is sent by the BME
108
to the CPU
102
. The CPU
102
then clears the control registers
110
and transmits a further set of control data to the register
110
.
It is a disadvantage of the system
100
that the CPU
102
is required to update the control registers
110
with new control data for the BME
108
at frequent intervals. In addition, since the tasks carried out by the BME
108
do not take equal amounts of time to perform, the CPU
102
is often required to wait for each task to finish before setting the registers for the next task.
SUMMARY OF THE INVENTION
The present invention concerns a data processing system comprising a block move engine, a memory, a register and a reader. The block move engine may be configured to process data. The memory may be configured to store data in the form of a linked list comprising a plurality of items of control data. The register may be associated with the block move engine and configured to control the block move engine, in response to the control data. The reader may be configured to read the control data from the memory and apply the control data to the register.
The objects, features and advantages of the present invention include providing a BME that may (i) operate substantially independently of the CPU, (ii) allow the CPU to carry out other functions and/or (iii) improve processor efficiency and performance.
REFERENCES:
patent: 4837447 (1989-06-01), Pierce et al.
patent: 4845656 (1989-07-01), Nishibe et al.
patent: 6020901 (2000-02-01), Lavelle et al.
Gibbon Stephen John
Pether David Neil
Christopher P. Maiorana P.C.
LSI Logic Corporation
Tung Kee M.
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