Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2011-01-11
2011-01-11
Elmore, Stephen C (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S168000, C710S110000
Reexamination Certificate
active
07870347
ABSTRACT:
The disclosed data processing system comprises a memory means (SDRAM), a plurality of data processing means (IP) provided for accessing to said memory means (SDRAM), and a communication interface means coupled between said memory means (SDRAM) and said plurality of data processing means (IP), said communication interface means including a network of nodes (H11, H12, H2), each node comprising at least one slave port (s) for receiving a memory access request from a data processing means (IP) or from a previous node and at least one master port (m) for issuing a memory access request to a next node or to said memory means (SDRAM) in accordance with the memory access request received at said slave port (s), wherein said at least one slave port (s) is connected to a master port (m) of a previous node or to one of said data processing means (IP) and said at least one master port (m) is connected to a slave port (s) of a next node or to said memory means (SDRAM).
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International Search Report of International Application No. PCT/IB2004/051491 Contained in International Publication No. WO2005026964.
Boonstra Johannes
Van Der Wolf Pieter
Van Eijndhoven Josephus Theodorus Johannes
Elmore Stephen C
Giardino, Jr. Mark A
Koninklijke Philips Electronics , N.V.
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