1996-10-02
1997-11-18
Harvey, Jack B.
395280, 395555, G06F 1300
Patent
active
056896581
ABSTRACT:
A data processing system has a processor, a RAM, an arithmetic unit, an address bus, a data bus, a state unit, and a bus controller. The state unit checks a front half and a rear half of a bus cycle of the processor, and generates a control signal indicating the front half and the rear half of the bus cycle. The bus controller receives the control signal, and based on the received control signal, indicates to the arithmetic unit receiving data transmitted from the RAM during the front half of the bus cycle, and to the processor receiving data transmitted from the arithmetic unit during the rear half of the bus cycle through the data bus.
REFERENCES:
patent: 4617642 (1986-10-01), Clark
patent: 4648102 (1987-03-01), Riso et al.
patent: 5450458 (1995-09-01), Price et al.
Harvey Jack B.
Kabushiki Kaisha Toshiba
Wiley David A.
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