Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-23
2003-01-14
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S097000, C700S105000, C700S120000, C700S121000, C430S005000, C378S035000, C382S144000
Reexamination Certificate
active
06507944
ABSTRACT:
BACKGROUND OF THE INVENTION
1. [Field of the Invention]
The present invention relates to data processing methods and apparatus, exposing methods and apparatus, recording media that stores programs for implementing the above methods and apparatus by function of software, and reticle masks made according to the above data processing methods, particularly to apparatus and methods for making reticle mask data (exposure data, check data, and verification data) from design data for manufacturing LSIs such as semiconductor devices, magnetic devices, liquid crystal devices, or printed circuit boards, and methods of performing exposure according to the reticle mask data.
2. [Description of the Related Art]
In a manufacturing process of LSIs such as semiconductor devices, design data that symbolically represents the circuit layouts on each semiconductor device to be manufactured, is first prepared by CAD (Computer-Aided Design) or the like. Data of a reticle, a photomask, or the like, (reticle mask data) representing a layout pattern used as an original for processing wafers, is then made on the basis of the design data. A photosensitive material is exposed according to the reticle mask data to make a reticle mask. The reticle mask is used for printing on wafers.
FIG. 1
is a block diagram showing a conventional data processing apparatus for making reticle mask data from design data. Referring to
FIG. 1
, the data processing apparatus
200
performs data processing to CAD data
1
, which symbolically represents circuit layouts, to make reticle mask data
2
. In accordance with the obtained reticle mask data
2
, an exposing apparatus (not shown) performs exposure to make a reticle mask
3
.
At first in the data processing apparatus
200
, an apparatus grid data calculation section
6
calculates grid data on the basis of reticle accuracy data
4
and processing parameters
5
being input. The grid data is used for determining the basic size of the layout pattern of the reticle mask data
2
when the reticle mask data
2
is made from a circuit layout in the CAD data
1
.
The grid data is made in the permissible minimum actual size in accordance with the minimum grid when the CAD data
1
is made, accuracy in pattern size on the reticle mask
3
, etc. More specifically, the grid data is made such that every edge of the pattern data of any circuit element constituting the reticle mask data
2
, is at a lattice point of the matrix defined according to the basic size set by the grid data.
The above-mentioned reticle accuracy data
4
gives information on permissible range of error in printing on wafers with the reticle mask
3
being made. The above-mentioned processing parameters
5
include various data such as layer composition data, sizing data, and scale data, which will be described below.
The layer composition data gives information on layer groups in case of dividing circuit patterns to make up the aimed semiconductor device, into layers in accordance with the roles and features of the circuit patterns, processing technique, conditions, etc. That is, the layer composition data gives information as to which layer each circuit pattern belongs to.
The sizing data gives information on size of each circuit pattern contained in the CAD data
1
. The scale data gives information on scale of enlargement of the whole semiconductor chip represented by the CAD data
1
. More specifically, the reticle mask data
2
is made by enlarging the CAD data
1
in accordance with the scale given by this scale data. Printing with the reticle mask
3
made according to the reticle mask data
2
, is performed with reduction to the same scale as that of the original CAD data
1
.
Next, an internal format conversion section
7
converts necessary one or ones of the CAD data
1
, the reticle accuracy data
4
, the processing parameters
5
, and the grid data calculated by the apparatus grid data calculation section
6
, into data
8
in accordance with the internal format of the data processing apparatus
200
. A logical operation processing section
9
then performs logical operation to the converted internal format data
8
to perform processing of layer composition, sizing, enlargement, or the like, given by the processing parameters
5
. Operated internal format data
10
is thereby made.
A format conversion/output section
11
then converts, in format, the operated internal format data
10
thus obtained, into data for exposing, and outputs it. The reticle mask data
2
is thereby made. The reticle mask data
2
thus obtained is circuit pattern data miniaturized according to the basic size of the grid data. Processing technique of, e.g., printing, varies in accordance with difference in the basic size of the pattern data.
The reticle mask data
2
made in the above data processing apparatus
200
, includes check data and verification data in addition to the exposure data as described above. The check data is layout data for checking whether the circuit pattern formed on a substrate on the basis of the exposure data, has its correct pattern. This check data is made in the same process as the exposure data. The verification data is layout data for verifying on data whether the obtained reticle mask data
2
has its correct pattern, in a stage prior to printing on the substrate. This verification data is also made in the same process as the exposure data.
Recent development of LSI is being larger-scale with advance in CAD tool, and the term for development is requested to be short. With this, it is requested to put quickly a large number of high-quality LSIs on the market. For this purpose, there has arisen the necessity of making each reticle mask with high accuracy used as a base in manufacturing semiconductor chips, in a short time, and of shortening the time for making reticle check data and verification data.
In a conventional technique of making reticle mask data, however, grid data is made in the permissible minimum actual size according to a mask design rule. So, even when each semiconductor chip being manufactured, includes a circuit pattern requiring not so high accuracy in grid, grid data is made with equally minute accuracy (small basic size).
As a result, processing time for making reticle mask data using the grid data, becomes long, besides, processing time for actually performing exposure, printing, comparative check, or data verification, on the basis of the obtained reticle mask data, also becomes long. These are problems.
Besides, particularly in a development process of a semiconductor device, design change in circuit or condition may be done, e.g., for improving the performance of the device. Such change brings change in layout pattern of, e.g., a reticle or a photomask.
FIG. 2
is a flowchart showing an outline of a process for making a reticle (reticle mask) on the basis of design data.
FIG. 2
shows the process of making a first reticle and the process of making a revised reticle.
At first, first design data
101
representing the layout pattern of a reticle is made with CAD. Data processing
111
is performed to the first design data
101
to make exposure data
102
. Data processing
111
includes conversion of the first design data
101
into internal format data, figure logical operation, sizing, etc. The exposure data
102
thus obtained is output to a recording medium (not shown) and stored therein.
The obtained exposure data
102
is then supplied to an exposing apparatus, wherein exposure
112
of a resist and then etching are performed. A reticle
103
is thereby made. Printing
113
on a glass substrate is then performed with the reticle
103
. A wafer
104
is thereby made. The wafer
104
thus obtained is subjected to a test
114
for, e.g., judging whether the circuit pattern formed on the substrate has its correct pattern, or examining the performance of the circuit pattern. When the conditions are satisfactory, the reticle completion
106
is confirmed.
If there is the necessity of, e.g., improving the performance, revise
115
of the design data
Ilduka Yoshimasa
Kikuchi Kenji
Minemura Masahiko
Okada Tomoyuki
Kik Phallaka
Smith Matthew
Staas & Halsey , LLP
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