Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-08-30
2002-05-28
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S102000, C711S104000
Reexamination Certificate
active
06397317
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data processing method and an apparatus having address conversion, which makes it possible to transfer data stored in a memory accessing at low speed to a memory accessing at high speed to perform high-speed accessing.
2. Description of the Related Art
Recently, there is a demand for a system, for example a printer, which performs data processing at high speed. However, since a ROM (read-only memory) for storing programs accesses data at low speed, there is such a problem that even if a central processing unit (CPU) can be used at high speed, there is a latency, thus requiring long access time. Therefore, to solve this problem, there is known a technique to realize a system in which a program is loaded to a high-speed RAM (random access memory) such as static RAM, DRAM having functions of page mode and hyperpage mode and the like, and the RAM is accessed to perform a high-speed processing. As follows is a description of the related art.
Related Art 1
In Japanese Patent Application Laid-open No. Hei 9-160824, there is disclosed a data processor which reads out program data from a read-only memory such as ROM to perform the processing. This is to transfer program data stored in a ROM generally known as low-speed access to a RAM known as high-speed access, at the time of initialization, and to access the program data normally from the RAM at high speed.
FIG. 1
is a schematic structural diagram disclosed in Japanese Patent Application Laid-open No. Hei 9-160824.
In
FIG. 1
, when a start signal is input to a timing generator
804
at the time of initialization, an address for accessing a low-speed ROM
806
is generated by an address generator
805
, using a timing produced by the timing generator
804
.
The n-bit address output from the address generator
805
is input to the ROM
806
and also a multiplexor
802
, and selected as an address output from an address generator
801
normally used, by a select signal slct output from the timing generator
804
, and output from the multiplexor
802
.
Therefore, at the time of initialization, the address from the address generator
805
is selected as an address for RAM
803
, and m-bit data read out from the ROM
806
is written in the RAM
803
.
On the other hand, at the normal situation, the address from the address generator
801
is selected, and the RAM
803
outputs program data based on the address. Hence, at the time of initialization, data from the low-speed ROM
806
is transferred to the RAM
803
, and at the normal situation, data is accessed from the RAM
803
.
Related Art 2
A technique for selecting an area in ROM and an area in RAM is disclosed in Japanese Patent Application Laid-open No. Hei 6-223205.
FIGS. 2 and 3
are schematic structural diagrams disclosed in Japanese Patent Application Laid-open No. Hei 6-223205.
In
FIG. 2
, two address setup registers
901
and
902
set up an address boundary between ROM (or SRAM) and DRAM in a memory map in
FIG. 3
, to set up [400000H] and [B00000H] (hexadecimal notation), respectively. With two comparator circuits
903
and
904
, addresses input by the address setup registers
901
and
902
and address input via an address bus are compared in size, and it is recognized by a judgement circuit
905
that memory map have been divided into three address areas as shown in FIG.
3
.
With three configuration registers (CR)
906
,
907
and
908
, it is configured that the three addresses are either for ROM (SRAM) or for DRAM. That is to say, a bit configuration is performed such that CR
906
is ROM, CR
907
is DRAM, and CR
908
is ROM. With the output from the judgement circuit
905
and the value configured by these three registers, a selection circuit
909
then sends the information showing which memory area is ROM, and which memory area is DRAM to a control circuit
911
.
When the address is in the area of DRAM in the control circuit
911
, a control signal for the DRAM is generated, and the address is divided into a column address and a row address by the multiplexor
910
and is output.
On the other hand, when the address is in the area of ROM, a control signal for the ROM is generated from the control circuit
911
, and the address is output directly.
Hence, which one of ROM and DRAM is used can be freely configured only by setting up the address setup registers
901
and
902
, and the configuration registers
906
,
907
and
908
.
Moreover, with this technique, address conversion is also possible. For example, by setting up the configuration registers
906
,
907
and
908
,
FIG. 3A
can be converted to
FIG. 3B
, and it looks like the address is converted.
Related Art 3
As a technique for performing the address conversion, there is known a technique disclosed in Japanese Patent Application Laid-open No. Sho 60-91460.
FIG. 4
is a schematic structural diagram disclosed in Japanese Patent Application Laid-open No. Sho 60-91460.
In
FIG. 4
, an address output from a central processing unit (hereinafter referred to as “CPU”)
1101
is transferred to an address detection circuit
1103
, and when it agrees with a preset address, the agreement is informed to a gate circuit
1104
.
Upon reception of the agreement information, the gate circuit
1104
opens the gate to output the data set in the offset register
1102
.
The adder
1105
adds the data from the gate circuit
1104
and the address from the CPU
1101
and outputs the converted address.
When the address detection circuit
1103
judges that the address from the CPU
1101
does not agree with the preset address, the gate circuit
1104
does not open the gate and outputs “0”. Thus, the adder
1105
will add the address from the CPU
1101
and “0”, that is, the original address which has not been converted is output.
With Japanese Patent Application Laid-open No. Hei 9-160824 of the related art 1, since it is so set that read is always performed from RAM at the normal situation, the RAM capacity for storing the transferred ROM data is generally required in addition to the working RAM required for the system. Hence, it has such defects that the system cost increases, and that the ROM is required only at the time of initialization, thus it is not efficient in view of the system efficiency.
With Japanese Patent Application Laid-open No. Hei 6-223205 of the related art 2, the address for ROM (SRAM) and the multiplexed address for DRAM is changed over from the common address bus to simplify the outside circuit. To realize a high-speed access, however, recently it is normal to constitute the system such that the ROM address and the DRAM address are separately set to make it possible to access them at the same time. The related art 2 has a defect in that such a construction is not considered.
As an effect of the related art 2, the address is converted, for example, from
FIG. 3A
to
FIG. 3B
, by transferring the ROM data in the memory area from the address [000000H] to [3FFFFFH] to the DRAM area from [400000H] at the time of initialization, so that an access from the high-speed DRAM is made possible. In this case, however, the access which has directly addressed the DRAM area before the conversion becomes impossible. For example, in the case where it is programmed to write [500000H] before the conversion, it has such a problem that [500000H] after the conversion becomes ROM, thereby write of [500000H] is not possible.
With Japanese Patent Application Laid-open No. Sho 60-91460 of the related art 3, the address is monitored by the address detection circuit
1103
, and when the address agrees with the predetermined address, the gate circuit
1104
is opened to add an offset value to the address. Hence, the time for agreement detection and the time for addition are required, which has a problem that a high-speed conversion is not possible.
SUMMARY OF THE INVENTION
With a view to solving the above-described problems, it is an object of the present invention to pro
Conlin David G.
Dike Bronstein Roberts & Cushman IP Group Edwards & Angell LLP
Kim Matthew
Peugh B. R.
Pledger Timothy Carter
LandOfFree
Data processing method and apparatus having address conversion does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data processing method and apparatus having address conversion, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data processing method and apparatus having address conversion will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2850731